1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to an electrically erasable programmable read only memory ("EEPROM") cell.
2. Description of Related Art
The semiconductor community faces increasingly difficult challenges as it moves into production of semiconductor devices at feature sizes approaching 0.1 micron. Cell designs for typical semiconductor devices must be made more reliable, scalable, cost effective to manufacture and able to operate at lower power in order for manufacturers to compete in the semiconductor industry. EEPROM devices are one of such semiconductor devices that must meet these challenges.
EEPROM devices are generally known as read-only memory in which the memory cells that store information may be erased and reprogrammed electrically. An EEPROM cell is typically made up of three separate transistors, namely, a write transistor, a sense transistor and a read transistor. The EEPROM cell is able to be programmed, erased and read by removing or adding electrons to a floating gate. Thus, for example, the floating gate may be programmed by removing free electrons from the floating gate and thereby giving the floating gate a positive charge. When it is desired to erase an EEPROM cell, the floating gate is given a net negative charge by injecting electrons onto the floating gate. The read operation is performed by reading the state (current) of the sense transistor. In order to give the floating gate a positive charge (program) or negative charge (erase), electron tunneling, for example using the well-known Fowler-Nordheim tunneling technique, may be performed by applying the appropriate voltage potentials between the floating gate and a region, such as a drain region, of a transistor. Upon applying the appropriate voltage potentials, electron tunneling occurs through a tunnel oxide layer between the floating gate and the region.
As the feature sizes of EEPROM cells are scaled downward, the prior art EEPROM cells exhibit certain scaleablity, cost and reliability limitations. First, the manufacturing process for a smaller EEPROM cell becomes more complex and, accordingly, manufacturing costs rise as transistor channel lengths are reduced. For example, as the channel length of a transistor of the EEPROM cell is scaled downward, the thickness of the gate oxide overlying the channel must also be reduced since the gate oxide thickness must be scaled with the channel length. In view of the fact that EEPROM cells already have a complex process to form multiple oxide thicknesses, additional oxide thicknesses for the transistors would add additional steps to further complicate the manufacturing process and thereby increase manufacturing costs.
Furthermore, in previous EEPROM cells, N conductivity type substrates were used which made operating the EEPROM cell more difficult. The difficulty arose from having to apply a bias to the N conductivity type substrate (difficult to perform) to prevent forward biasing of a P-well/N conductivity type substrate containing a tunneling transistor used to operate the EEPROM cell. The N conductivity type substrates are also not commonly used while P conductivity type substrates are predominately used in the semiconductor industry. A need therefore exists for an EEPROM cell using a P conductivity type substrate.
In addition to these scaling and operating problems, reliability problems also exist with previous EEPROM cells. First, the EEPROM cell is typically both programmed and erased through the same small tunnel oxide window at the edge of a transistor region that may deteriorate the cell quickly. In general, the tunnel oxide window deteriorates after tens of thousands of program/erase cycles and that deterioration cycle is shortened by only using the small tunnel oxide window for both programming and erasing operations. Thus, in addition to the size of the tunnel oxide window, the use of the window for both programming and erasing of the EEPROM cell causes the cell to be significantly less reliable. A further reliability limitation of previous EEPROM cells is that the tunnel oxide window is often less reliable because it is formed over a highly doped program junction (PRJ). The high doping concentration of the PRJ degrades the oxide immediately above the PRJ and thereby reduces the EEPROM cell's reliability. A still further limitation of the EEPROM cell is that the voltages needed to program, erase and read the cell are high due to the relatively large feature sizes of the cell. Thus, in order to achieve lower voltages to operate the EEPROM cell, feature sizes of the cell must be scaled downward.
Thus, a need exists for a redesigned EEPROM cell that (1) does not add costly steps to the manufacturing process, (2) does not suffer from reliability problems caused by programing and erasing through the edge of a small tunnel oxide window, (3) does not deteriorate through use of a PRJ oxide, (4) operates at a lower power by using smaller feature sizes and (5) is formed in a P conductivity type substrate to avoid forward biasing and substrate availability problems.